In modern semiconductor device applications, numerous individual devices are packed onto a single small area of a semiconductor substrate. Many of these individuals devices need to be electrically isolated from one another. One method of accomplishing such isolation is to form a trenched isolation region between adjacent devices. Such trenched isolation region will generally comprise a trench or cavity formed within the substrate and filled with an insulative material, such as, for example, silicon dioxide. Trench isolation regions are commonly divided into three categories: shallow trenches (trenches less than about one micron deep); moderate depth trenches (trenches of about one to about three microns deep); and deep trenches (trenches greater than about three microns deep).
Prior art methods for forming trench structures are described with reference to FIGS. 1-9. Referring to FIG. 1, a semiconductor wafer fragment 10 is shown at a preliminary stage of a prior art processing sequence. Wafer fragment 10 comprises a semiconductive mate rial 12 upon which is formed a layer of oxide 14, a layer of nitride 16, and a patterned layer of photoresist 18. Semiconductive material 12 commonly comprises monocrystalline silicon which is lightly doped with a conductivity-enhancing dopant. To aid in interpretation of the claims that follow, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Semiconductive material 12 comprises an upper surface 15. Oxide layer 14 is formed over upper surface 15 and typically comprises silicon dioxide. Nitride layer 16 is formed over oxide layer 14 and typically comprises silicon nitride. Oxide layer 14 is typically from about 50 Angstroms to about 300 Angstroms thick, and nitride layer 16 is generally from about 400 Angstroms thick to about 2000 Angstroms thick.
Referring to FIG. 2, patterned photoresist layer 18 is used as a mask for an etching process. The etch is typically conducted utilizing dry plasma conditions and CH.sub.2 F.sub.2 /CF.sub.4 chemistry. Such etching effectively etches both silicon nitride layer 16 and pad oxide layer 14 to form openings 20 extending therethrough to expose a portion of substrate 12. The etching stops upon reaching silicon substrate 12. After the etch of nitride layer 16, nitride layer 16 becomes a masking layer for subsequent processing of wafer fragment 10.
Referring to FIG. 3, a second etch is conducted to extend openings 20 into silicon substrate 12. The second etch is commonly referred to as a "trench initiation etch." A purpose of such trench initiation etch can be to clean an exposed surface of silicon substrate 12 within openings 20 (i.e., to remove defects and polymer material) prior to final trenching in to substrate 12. The trench initiation etch is typically a timed dry plasma etch utilizing CF.sub.4 /HBr. The trench initiation etch typically extends openings 20 to less than or equal to about 500 Angstroms into substrate 12.
Referring to FIG. 4, a third etch is conducted to extend openings 20 further into substrate 12 and thereby form trenches within substrate 12. The third etch typically utilizes an etchant consisting entirely of HBr, and is typically a timed etch. The timing of the etch is adjusted to form trenches within substrate 12 to a desired depth. For instance, if openings 20 are to be shallow trenches, the third etch will be timed to extend openings 20 to a depth of less than or equal to about one micron.
Referring to FIG. 5, photoresist layer 18 (FIG. 4) is removed, and an oxide material 24 is formed within opening 20 (FIG. 4) and over nitride layer 16. Oxide material 24 can be formed by, for example, initially forming a thin layer of oxide (50 Angstroms to 150 Angstroms thick) through thermal oxidation of substrate 12 within opening 20 (FIG. 4), and subsequently providing high-density plasma oxide to fill opening 20 and overlie nitride layer 16.
Referring FIG. 6, wafer fragment 10 is subjected to planarization (such as, for example, chemical-mechanical polishing) to planarize an upper surface of oxide material 24 (FIG. 5). Nitride layer 16 functions as an etch-stop during such planarization. The oxide material 24 (FIG. 5) remaining within opening 20 (FIG. 4) after the planarization is an oxide plug 30.
Referring to FIG. 7, nitride layer 16 (FIG. 6) is removed. An exemplary process for removing layer 16 is a wet etch utilizing HF, followed by hot H.sub.3 PO.sub.4.
Referring to FIG. 8, oxide layer 14 (FIG. 7) is removed. An exemplary process for removing layer 14 is a wet etch utilizing HF. As shown, the wet etch has removed portions of oxide plug 30 to recess edges of plug 30 beneath upper surface 15 of substrate 12. Accordingly, gaps 32 are formed between upper surface 15 of substrate 12 and oxide plug 30. More specifically, insulative plug 30 comprises peripheral sidewalls 35 having portions 40 extending below substrate upper surface 15 of substrate 12 and portions 42 above upper surface 15. Portions 40 comprise lower segments 44 which are against substrate 12 and upper segments 46 which are separated from substrate 12 by gaps 32.
Referring to FIG. 9, an oxide layer 34 is grown over upper surface 15 (by, for example, thermal oxidation), and a polysilicon layer 38 is formed over oxide layer 34. Polysilicon layer 38 can be formed by, for example, chemical vapor deposition. Polysilicon layer 38 can ultimately be formed into a wordline comprising transistor gate regions adjacent oxide plug 30. Plug 30 then functions as a trenched isolation region. Gaps 32 can undesirably result in formation of parasitic devices adjacent the transistor devices and ultimately have an effect of lowering a threshold voltage for the transistor devices. Accordingly, it would be desirable to alleviate gaps 32. Gaps 32 can also interfere with subsequent fabrication processes. For this reason as well, it would be desirable to alleviate gaps 32.